Advanced Computer Architecture--- IIIrd Internal

1) Define amdahl's law and calculate overall speedup using amdahl's law. Given that a new CPU, which is 20 times faster than the original CPU, on computation, is additionally introduced, the original CPU is busy with computations 80% of the time and an i/o time is 80.

2) Define the dependability?

Assume a disk subsystem with following components and an MTTF.

-> 10 disks, each rated at 1,000,000 hours MTTF

-> 1 SCSI controller, 500,000 hours MTTF

->1 power supply, 200,000 hours MTTF

-> 1 fan, 200,000 hours MTTF

-> 1 SCSI cable 1,000,000 hours MTTF

Find the sum of Failure rate of the computer system and the overall MTTF of the system?

3) What are the trends in cost? Find the no of dies in a 300mm(30 cm) wafer for dies that is 1.5 cm on a side?

4) What are the trends in power technology? Find the die yield for dies that are 1.5 cm on a side and 1.0 cm on other side. Assume the defect density is 0.4 /cm² and α is 4.

5) Explain the control hazard under the different clock cycles?

6) Explain the data dependencies and draw the graph for trends in technology?

7) Explain the addressing modes?

8) Explain dynamic branch prediction? And explain correlating branch predictors?

9) Explain overcoming data hazards with dynamic scheduling?

10) Draw a diagram of the basic structure of a MIPS floating point unit using Tomasulo’s algorithm with a few points explanation.

EMBEDDED COMPUTING SYSTEMS-QUESTION BANK-IIIrd Internal

EMBEDDED COMPUTING SYSTEMS

QUESTION BANK

UNIT – 6

1. CASE STUDY: Telephone Answering Machine. Write the Theory of operation and requirements along with detailed specifications. 10 Marks
2. Explain briefly the procedure of evaluating operating system performance.10M
3. Describe various interprocess communication mechanisms. 10 Marks
4. Explain Power Management and optimization for processes. 10 Marks
5. Describe the following: I) CPU Metrics 5 Marks II) Timing requirements on process. 5 Marks

UNIT- 7

6. CASE STUDY: Elevator Controller. Write the Theory of operation and requirements and architecture of elevator system. 10 Marks
7. what is Internet? Describe Internet-Enabled systems in detail. 10 Marks
8. What is Ethernet? Describe its functionalities in detail. 10 Marks
9. Describe commonly used embedded networks in detail 10 Marks
10. Describe network abstraction and message passing programming in distributed embedded architectures. 10 Marks
11. Explain the hardware and software architectures of distributed embedded architectures. 10 Marks
12. Define Automotive Networks with Example briefly. 10Marks
13. How do we design a Distributed embedded system around a network. 10 Marks
14. Describe various Networks used for Embedded systems and explain I²C BUS in detail 10 Marks.
15. With a neat sketch, explain the CAN data frame format and typical bus transactions on the IC bus. 10 Marks
16. Explain Ethernet format and IP structure 10 Marks

EMBEDDED COMPUTING SYSTEM - 10CS72                   
                     UNIT – 5 RTOS- I
(questions struck off are not there)
1)    What is RTOS? Explain the Basic functionalities used in Operating systems. 10 Marks
2)    Explain different types of Operating systems. 10 Marks
3)    Compare Threads and Process in detail. 10 Marks
4)    Differentiate the following: Threads and Process and explain Thread preemption.10 Marks
5)    Explain the factors for selecting a scheduling criterion/algorithm in Task scheduling process. 10 Marks
6)    Explain the following Non-preemptive scheduling Process: i) FCFS/FIFO scheduling. 5Marks ii) LCFS/LIFO  scheduling.  5Marks
7)    Explain the following Non-preemptive scheduling: i) SJF scheduling. 5Marks ii) Priority Based scheduling. 5Marks
8)    Explain the following preemptive scheduling Process: i) Preemptive SJF scheduling/SRT. 5Marks ii) Round Round (RR) scheduling.  5Marks
9)    Explain Shared Memory Process in detail. 10 Marks
10)    Explain Message Passing system in detail. 10 Marks
11)    What is a deadlock? Explain where deadlock situation can arise and methods to avoid deadlocks. 10 Marks
12)    Explain Dining Philosopher's Problem in detail. 10 Marks
13)    Explain Producer-Consumer/Bounded Buffer Problem. 10 Marks
14)    Explain Task synchronization Techniques. 10 Marks
15)    Describe SEMOPHORE in detail. 10 Marks
16)    Explain the role of Device driver in Embedded OS based Products.And describe the functional and non-functional requirements in using an RTOS. 10 Marks
17)    Three Processes with process ID's P1,P2,P3 with estimated completion time 10,5,7 milliseconds respectively enters the ready queue together in order P1,P2,P3. Calculate the Waiting time and Turn Around Time(TAT) for each process and the Average Waiting time and Turn Around Time(TAT) (Assuming there is no I/O waiting for the processes) in the FIFO scheduling. 10 Marks
18)    Three Processes with process ID's P1,P2,P3 with estimated completion time 6,4,2 milliseconds respectively enters the ready queue together in order P1,P2,P3. Calculate the Waiting time and Turn Around Time(TAT) for each process and the Average Waiting time and Turn Around Time(TAT) (Assuming there is no I/O waiting for the processes) in RR algorithm with Time slice = 2ms. 10 Marks
19)    Three Processes with process ID's P1,P2,P3 with estimated completion time 12,10,2 milliseconds respectively enters the ready queue together in order P2,P3,P1. A new process P4 with estimated execution completion time 4 milliseconds enters the ready queue enters the ready queue after 8 milliseconds. Calculate the Waiting time and Turn Around Time(TAT) for each process and the Average Waiting time and Turn Around Time(TAT) (Assuming there is no I/O waiting for the processes) in the Non-preemptive LIFO scheduling. 10 Marks.
20)    Three Processes with process ID's P1,P2,P3 with estimated completion time6,8,2
milliseconds respectively enters the ready queue together . A new process P4 with estimated execution completion time 4 milliseconds enters the ready queue enters the ready queue after 1 milliseconds. Calculate the Waiting time and Turn Around Time(TAT) for each process and the Average Waiting time and Turn Around Time(TAT) (Assuming there is no I/O waiting for the processes) in the Non-preemptive SJF scheduling. 10 Marks.
21)    Three Processes with process ID's P1,P2,P3 with estimated completion time 4,6,5
milliseconds and priorities 1,0,3 (0--Highest priority and 3-- Lowest priority) respectively enters the ready queue together. A new process P4 with estimated execution completion time 6 milliseconds and priority 2 enters the ready queue enters the ready queue after 5 milliseconds. Calculate the Waiting time and Turn Around Time(TAT) for each process and the Average Waiting time and Turn Around Time(TAT) (Assuming there is no I/O waiting for the processes) in the Non-preemptive Priority-Based scheduling. 10 Marks.
22)    Three Processes with process ID's P1,P2,P3 with estimated completion time 4,6,5
milliseconds and priorities 1,0,3 (0--Highest priority and 3-- Lowest priority) respectively enters the ready queue together. Calculate the Waiting time and Turn Around Time(TAT) for each process and the Average Waiting time and Turn Around Time(TAT) (Assuming there is no I/O waiting for the processes) in the Preemptive Priority-Based scheduling. 10 Marks.
23) Three Processes with process ID's P1,P2,P3 with estimated completion time 12,10,6
milliseconds respectively enters the ready queue together . A new process P4 with estimated execution completion time 2 milliseconds enters the ready queue enters the ready queue after 3 milliseconds. Calculate the Waiting time and Turn Around Time(TAT) for each process and the Average Waiting time and Turn Around Time(TAT) (Assuming there is no I/O waiting for the processes) in the SRT scheduling. 10 Marks.


                        UNIT – 6 RTOS-II

    1) CASE STUDY: Telephone Answering Machine. Write the Theory of operation and             requirements along with detailed specifications. 10 Marks
    2) Explain briefly the procedure of evaluating operating system performance. 10 Marks
    3) Describe various interprocess communication mechanisms. 10 Marks
    4) Explain Rate-Monotonic scheduling under priority based scheduling. 10 Marks
    5) Explain Earliest-Deadline-First scheduling under priority based scheduling. 10 Marks
    6) Describe various platforms under preemptive Real-time operating systems and              explain any two in detail. 10 Marks
    7) Describe the following: I) CPU Metrics 5 Marks  II)Timing requirements on process.              5 Marks
    8) Define Tasks and process. Explain Multirate systems. 10 Marks

Advanced Computer Architecture-IInd Internal Question Bank

Unit-5

1) Explain the computer structures of SISD, SIMD, MISD and MIMD with a neat diagram.

2) What is distributed shared memory architecture?

3) What is symmetric shared memory architecture? Explain with a block diagram.

4) Explain bus snooping protocols with block diagram.

5) Explain state diagram for a cache block in directory based system.

Unit-6

6) Explain first and second optimization for increasing cache performance.

7) Explain the Third optimization in detail.

8) Explain the Fourth optimization in detail of a cache performance.

9) Explain the Fifth optimization in detail.

10) Explain the Sixth optimization in detail.

Question_Bank-Advanced_Computer_Architecture(ACA)-VTU-VII-A&B

Question Bank- ACA- VII A & B- 1st Internal

1) Explain various classes of computers? And the 7 dimensions of ISA?

2) Write a note on recent trends in computer design or explain trends in technology?

3) What is Amdahl’s law? Explain in detail with example?

4) What is trends in performance of parallel computers. Explain in detail.

5) How to measure and report the performance of the parallel computing systems?

6) What is a structural Hazard? Explain with a neat diagram?

7) What is a data hazard? Explain with a neat diagram?

8) What is control hazard? Explain with a neat diagram?

9) Explain the implementation of MIPS pipeline with a neat diagram?

10) What are the types of dependencies? Explain the data dependencies?

11) Explain the name dependencies?

12) Explain the control dependencies?

Information and Network Security - IIIrd Internal QB

Download

Hope this helps.

System Simulation and Modelling - IIIrd internal Question Bank

Final QB:

Download

Reduced number of questions from 19 to 14. They are from unit 6 and 8. 4 questions in unit 6 and 10 from unit 8.