Advanced Computer Architecture-Ist Internal

I have tried to remove duplicates as much as possible since my last post. There are now 30 unique questions out of which nearly 11 are problematic and remaining are descriptive. Pattern will be 1a,1b,1c ...4a,4b.

Unit-I

1) List and explain four important technologies which have led to the improvements in computer system.

2) Give a brief explanation about trends in power in integrated circuits and cost.

3) Define computer architecture. Illustrate the seven dimensions of an ISA.
3) Define the computer architecture. Explain the response time, throughput, elapsed time and processor clock.

4) Explain in brief measuring, reporting and summarizing performance of computer system.

5) Assume a disk subsystem with the following components and MTTF:

10 disks, each rated at 1000000- hour MTTF.

1 SCSI controller, 500,000- hour MTTF.

1 power supply, 200,000 – hour MTTF.

1 fan, 200,000 – hour MTTF.

1 SCSI cable, 1,000,000 – hour MTTF.

Using the simplifying assumptions that the lifetimes are exponentially distributed and that failures are independent,  compute the MTTF of the system as a whole.

6) Briefly explain the Amdhal’s law.
6) Define Amdahls law. Derive an expression for CPU clock as a function of instruction count, clocks per instruction and clock cycle time.

7) Two code sequences for a particular machine are considered by a compiler designer.

                                Instruction class                CPI for this instruction class

                                                A                                             1

                                                B                                             2

                                                C                                             3

The compiler designer considers 2 code sequences that require the following instruction counts for a particular high-level language statement

Code Sequence                Instruction counts for instruction class

                A             B             C

1              20           10           20

2              40           10           10

i)             Which code sequence executes most of the instruction?

ii)            What is the CPI for each sequence?

iii)           Which will be faster?

8) Explain with a learning curve, how the cost of processor varies with time along with factors influencing the cost.

9) Find the number of dies per 200cm wafer of circular shape that is used to cut die that is 1.5 cm side and compare the number of dies produced on the same wafer if the die is 1.25 cm.

10) The given data presents the power consumption of several computer system components:

Component        Product                Performance                     Power

Processor            Sun Niagara 8-core                          1.2 GHz 72-79 W

DRAM                   Kingston 1GB                              184-pin 3.7 W

Hard drive           Diamond Max 7200 rpm                7.9 W read 4.0 W idle

i)             Assuming the maximum load for each component, a power supply efficiency of 70%, what wattage must the server’s power supply deliver to a system with a Sun Niagara 8-core chip, 2GB 184-pin Kingston DRAM and 7200 rpm hard drives?

ii)            How much power will the 7200 rpm disk drive consume, if it is idle roughly 40% of the time?

iii) Assume that for the same set of requests, a 5400 rpm disk will require twice as much time to read data as a 10800 rpm disk. What percentage of time would the 5400 rpm disk drive be idle to perform the same transaction as in part (II)?

11) We will run two applications on dual Pentium processor, but the resource requirements are not the same. The first application needs 80% of the resources, and the other only 20% of the resources.

i) Given that 40% of the first application is parallelizable, how much speed up will we achieve with that application, if run in isolation?

ii) Given that 99% of the second application is parallelizable, how much speed up will this application observe, if run in isolation?

iii) Given that 40% of the first application is parallelizable, how much overall system speedup would you observe, if we parallelized it?

12) What is dependability? Explain two main measures of dependability.

13) Given the following measurements:

                Frequency of FP operations= 25%            Average CPI of FP operations=4.0

                Average CPI of other instructions=1.33  Frequency of FPSQR=2%

                CPI of FPSQR=20

Assume that  the two design alternatives are to decrease the CPI of FPSQR to 2 or to decrease the average CPI of all FP operations to 2.5. Compare the two design alternatives using the processor performance equations.

Unit-II

14) With a neat diagram, explain the classic five-stage pipeline for a RISC processor.

15) What are the  major hurdles of pipelining? Illustrate the branch hazards in detail.

15) What are the major hurdles in pipelining? Illustrate the data hazard, briefly.

16) List pipeline hazards. Explain any one in detail.
16) Explain the pipeline hazards, in detail.
16) What are the major hazards in a pipeline? Explain data hazard and methods to minimize data hazard with example.

17) List and explain five different ways of classifying exception in a computer system.

18) An unpipelined machine has 10ns clock cycle and it uses four cycles for ALU operations and branches, five cycles for memory operations. Assume that relative frequencies of these operations are 40%, 20% and 40% respectively. Suppose due to clock skew and setup, pipelining the  machine adds 1ns overhead to the clock. Find the speed up from pipelining.

19) Consider the following calculations:  x= y + z    ;  a= b * c.  Assume the calculations are done using registers. Show, using 5 stage pipeline, how many clock pulses are required for direct operations. By recording with stalls show how many clock pulses are required and saving in the number of clock pulses to solve data hazard.

20) Show java loop is unrolled so that there are four copies of the loop body, assuming R1-R2(that is, the size of the array) is initially a multiple of 32, which means that the number of loop iterations is a multiple of 4. Eliminate any obvious redundant computations and do not reuse any of the registers.

21) Explain how pipeline is implemented in MIPS.
21) With a neat block diagram, explain how an instruction can be executed in 4 or 5 clock cycles in MIPS data path, without the pipeline register.

22) Explain different techniques in reducing pipeline branch penalties.

23) Consider the unpipelined processor in RISC. Assume that it has a 1ns clock cycle and that it uses 4 cycles for ALU operations and branches and 5 cycles for memory operations. Assume that the relative frequencies of these operations are 40%, 20% and 40% respectively. Suppose that due to clock skew and setup, pipelining the processor adds 0.2ns of overload to the clock. Ignoring any latency impact, how much speedup in the instruction execution rate will we gain from a pipeline?

Unit-III

24) What are the basic compiler techniques for exposing ILP? Explain briefly.

25) Explain true data dependence, name dependence and control dependence with an example code fragment.
25) What are data dependencies? Explain name dependences with example between two instructions.

26) List the steps to unroll the code and schedule.

27) What are the techniques used to reduce branch costs? Explain both static and dynamic branch prediction used for same.

28) Explain the dynamic branch prediction state diagram.
28) What is the drawback of 1-bit dynamic branch prediction method? Clearly state, how it is overcome in 2-bit prediction. Give the state transition diagram of 2-bit predictor.
28) What is dynamic prediction? Draw the state transition diagram for 2-bit prediction scheme?

29) What is correlating predictors? Explain with examples.

  

30) Show how the below loop would look on MIPS 5-stage pipeline, under the following situations. Find the number of cycles per iteration, for each case. Assume the latencies for integer and floating point operations, as given in the prescribed text book.

Loop:     L.D          F0,0(R1)

                ADD.D   F4,F0,F2

                S.D         F4,0(R1)

                DADDUI               R1,R1,#-8

                BNE        R1,R2, Loop

i)             Without scheduling and without loop unrolling.

ii)            With scheduling and without loop unrolling.

iii)           With loop unrolling four times and without scheduling.

iv)           With loop unrolling four times and with scheduling.

                                            ~~~~x0x~~~~