Thursday, December 4, 2014

Embedded Computing Systems-10CS72-Question PaperDec/Jan,2014

Since the VTU scheme changed to 2010 in Aug,2013 there are only two question papers to refer to. Dec/jan 2014 and June/July 2014.
(Word Format)

1 a) What is an embedded system? Explain the purpose of ES? List its major application areas
 and give one example for each.-8M
b) Differentiate the following, with an example:
i) Microprocessor and microcontroller  
ii) Embedded system and general purpose computers.-6M
c) Write a requirement chart for digital camera.-3M
d) List challenges of embedded computing system design. Explain briefly any two challenges. -3M

2 a) What are the major difference between Von neuman and Harward architecture?-4M
b) Explain the following:
i) Restrictions of MUL instruction.
ii) Uses of MLA instruction
iii) Register indirect addressing in ARM.
iv) Write a ARM assembly code for below C- statement z=(x|22) and (y>>2)
v) Disadvantages of busy-wait IO.-7M
c) What is an interrupt? Explain with neat diagram the interrupt mechanism.-5M
d) Solve the following:
i) What is the average memory access time of machine whose hit rate is 93% with cache
 access time of 5ns and main memory access time is 80ns.-4M
ii) Calculate cache hit rate, if the cache access time is 5ns, average memory access
 time is 6.5 ns and main memory access time is 80ns.-4M

3 a) Explain with a neat diagram, the bus with a DMA controller.-5M
b) Explain the following briefly:
I) Counter
ii) Watchdog Timer
iii) Break point
iv) Timer-4M
c) Differentiate PCI and USB by their characteristics.-3M
d) Assume that the bus has a 1MHz bus clock period, width is 2 bytes per transfer, data 
transfer itself takes 1 clock cycles, address and handshaking signals before data is 2 clock
 cycles and sending ACK after data is 1 clock cycles
i) What is the total transfer time in clock cycles to transfer a total 612000 bytes of data?
ii) What is the total burst mode transfer time in clock cycle, if B=2 byte with 2 byte wide
iii) Calculate the total real time to transfer data.-8M
4 a) Consider the following ARM assembly code, which illustrate some sample C statement.
LDR LDR ADD STR LDR LDR ADD STR LDR ADD STR LDR LDR SUB STR
r0,a R1,b R2,r0,r1 R2,w R0,c R1,d R2,r0,r1 R2,x R1,e R0,r1,r2 R0,u R0,a R1,b R2,r1,r0 R2,z
Answer the following:
I) Write the sample C code fragment for the above ARM assembly code.
ii) Draw a lifetime graph that shows uses of register in register allocation for the above 
C statement
iii) Modify the obtained C code statement using operator scheduling for register allocation
iv) Draw a lifetime graph for the modified 'C' code appear.
v) Write a ARM assembly code for the modified 'C' code using register allocation.-10M
b) Consider the following 'C' code segment
if(a>b)
x=a+b;
else x=a-b;
I) Write CDFG for the above 'C' statement
ii) Generate the ARM assembly code for the above 'C' statement.-7M
c) Explain briefly different types of performance measures on programs.-3M
Part-B
5 a) What is RTOS? Explain with an example the hard real time and soft real time.-6M
b) Differentiate process and threads. What are the parameters of PCB of a process? Why 
should each process have a distinct PCB?-8M
c) What is the significance of spin lock?-2M
d) What is semaphores? Explain briefly the different types of semaphores?-8M

6 a) Explain with neat diagram, the concept of memory mapped object.-8M
b) Explain the following:
I) Message passing
ii) Remote procedure call for IPC.-6M
c) What are the factors needs to be evaluated in selection of an RTOS? Explain.-6M

7 a) Explain with neat diagram the various fields of IP packet.-8M
b) List the features of internet LAN.-4M
c) With neat diagram, explain the various fields of CAN frame.-6M
d) Briefly explain any two features of HTTP protocols.-2M

8 a) Explain the following
I) Simulator
ii) Target system
iii) Debugging
iv) Logic analyzer-8M
b) Explain features advantages and limitations of simulator based debugging.-6M
c) Explain the types of multitasking.-6M
 
Typographical errors are regretted.... 

Sunday, November 30, 2014

Advanced Computer Architecture-June/July2014-VTU-Question Paper




1a) Define computer architecture. List and explain four important technologies, which lead to improvements in computer systems. 10M
b) Find the number of dies per 300 mm wafer for a die that is 1.5 cm on a side. 2M
c) Define Amdahls law. Derive an expression for CPU clock as a function of instruction count, clock per instruction and clock cycle time.-8M

2 a) List three major hurdles of pipelining. Explain the concept of minimizing data hazards stalls by forwarding. -10M
b) Briefly explain how the MIPS instructions can be implemented in at most five clock cycles. -5M
c) List and explain five different ways of classifying exceptions in a computer system.-5M

3a) What is instruction level parallelism? Explain control dependence using code fragment.-8M
3b) Explain the states in 2-bit prediction scheme used for dynamic branch prediction. -6M
3c) With a neat diagram, explain the basic structure of a MIPS floating point unit using Tomasulo's algorithm.-6M

4a) With a neat diagram, explain the four steps involved in executing instructions using hardware based speculation.-10M
b) What is branch target buffer? With a neat diagram, explain the steps when using branch target buffer for a simple five stage pipeline.-10M

5 a) To achieve a speedup of 80 with 100 processors what fraction of the original computation can be sequential?-4M
b) Explain the two cache coherence protocols used for enforcing coherence.-6M
c) Explain directory based cache coherence for a distributed memory multiprocessor system along with the state transition diagram.-10M

6 a) List and explain any four basic cache optimization techniques.-10M
b) With a neat diagram explain the translation buffer of fast address translation.-10M

7 a) List any five advanced optimizations of chache performance and explain briefly the compiler optimization to reduce miss rate.-10M
b) Explain briefly how memory protection is enforced via virtual memory and via virtual machines.-10M

8 a) Explain the architecture of IA64 intel processor and also the prediction and speculation support provided.-10M
b) Write short notes on benchmarks.-5M
c) Explain the internal organization of 64M bit RAM.-5M



Accuracy of the above question paper is not guaranteed.
View all units question bank(ACA from july2010 upto july2012).... here.

Embedded Computing Systems-10CS72-Question-Paper -June/July-2014



1a) Give the characteristics and constraints of embedded system.-4M
b) Explain the challenges in embedded computing system design.-8M
c) Define design methodology. Explain the embedded system design process.-8M

2a) Differentiate between the Harvard and von-Neumann architecture.-5M
b) Define ARM processor, Explain advanced ARM features.-7M
c) What is pipelining? Explain the C55x of a seven stages pipeline with a neat diagram of ARM instructions.-8M

3 a) Write the major components of bus protocol. Explain the burst read transaction with a timing diagram.-8M
b) Describe: I) Timer    ii) Cross compiler   iii) Logic analyzer.-6M
c) With a neat sketch, explain the glue logic interface.-6M

4a) Explain the circular buffers for embedded programs.-4M
b) With a neat sketch, explain the role of assemblers and linkers in compilation process.-8M
c) Explain with example, the techniques in optimizing. -8M


5 a) What is RTOS? List and explain the different services of RTOS.-10M
b) Describe the concept of multithreading and write the comparison between thread and process.-10M

6a) Define blocking and nonblocking communication. Explain the two styles of interprocess comminication, with a example.-10M
b) What are the assumptions for the performance of a real system running processes? Mention the factors that effect context switching time and interrupt latency.-10M

7a) With a neat sketch, explain the CAN data frame format and typical bus transactions on the I2C Bus.-10M
b) Explain the ethernet packet format and IP packet structure.-10M

8a) What is a simulator? Explain the features, advantages and limitations of simulator based debugging.-10M
b) What are the improvements over firmware software debugging? Explain.-10M

Accuracy of the above question paper is not guaranteed

Sunday, November 9, 2014

Advanced Computer Architecture--- IIIrd Internal

1) Define amdahl's law and calculate overall speedup using amdahl's law. Given that a new CPU, which is 20 times faster than the original CPU, on computation, is additionally introduced, the original CPU is busy with computations 80% of the time and an i/o time is 80.

2) Define the dependability?

Assume a disk subsystem with following components and an MTTF.

-> 10 disks, each rated at 1,000,000 hours MTTF

-> 1 SCSI controller, 500,000 hours MTTF

->1 power supply, 200,000 hours MTTF

-> 1 fan, 200,000 hours MTTF

-> 1 SCSI cable 1,000,000 hours MTTF

Find the sum of Failure rate of the computer system and the overall MTTF of the system?

3) What are the trends in cost? Find the no of dies in a 300mm(30 cm) wafer for dies that is 1.5 cm on a side?

4) What are the trends in power technology? Find the die yield for dies that are 1.5 cm on a side and 1.0 cm on other side. Assume the defect density is 0.4 /cm2 and α is 4.

5) Explain the control hazard under the different clock cycles?

6) Explain the data dependencies and draw the graph for trends in technology?

7) Explain the addressing modes?

8) Explain dynamic branch prediction? And explain correlating branch predictors?

9) Explain overcoming data hazards with dynamic scheduling?

10) Draw a diagram of the basic structure of a MIPS floating point unit using Tomasulo’s algorithm with a few points explanation.

Wednesday, November 5, 2014

EMBEDDED COMPUTING SYSTEMS-QUESTION BANK-IIIrd Internal


EMBEDDED COMPUTING SYSTEMS
QUESTION BANK

UNIT – 6



  1. CASE STUDY: Telephone Answering Machine. Write the Theory of operation and requirements along with detailed specifications. 10 Marks
  2. Explain briefly the procedure of evaluating operating system performance.10M
  3. Describe various interprocess communication mechanisms. 10 Marks
  4. Explain Power Management and optimization for processes. 10 Marks
  5. Describe the following: I) CPU Metrics 5 Marks II) Timing requirements on process. 5 Marks

UNIT- 7
  1. CASE STUDY: Elevator Controller. Write the Theory of operation and requirements and architecture of elevator system. 10 Marks
  2. what is Internet? Describe Internet-Enabled systems in detail. 10 Marks
  3. What is Ethernet? Describe its functionalities in detail. 10 Marks
  4. Describe commonly used embedded networks in detail 10 Marks
  5. Describe network abstraction and message passing programming in distributed embedded architectures. 10 Marks
  6. Explain the hardware and software architectures of distributed embedded architectures. 10 Marks
  7. Define Automotive Networks with Example briefly. 10Marks
  8. How do we design a Distributed embedded system around a network. 10 Marks
  9. Describe various Networks used for Embedded systems and explain I²C BUS in detail 10 Marks.
  10. With a neat sketch, explain the CAN data frame format and typical bus transactions on the IC bus. 10 Marks
  11. Explain Ethernet format and IP structure 10 Marks

Monday, October 13, 2014

EMBEDDED COMPUTING SYSTEM - 10CS72                   
                     UNIT – 5 RTOS- I
(questions struck off are not there)
1)    What is RTOS? Explain the Basic functionalities used in Operating systems. 10 Marks
2)    Explain different types of Operating systems. 10 Marks
3)    Compare Threads and Process in detail. 10 Marks
4)    Differentiate the following: Threads and Process and explain Thread preemption.10 Marks
5)    Explain the factors for selecting a scheduling criterion/algorithm in Task scheduling process. 10 Marks
6)    Explain the following Non-preemptive scheduling Process: i) FCFS/FIFO scheduling. 5Marks ii) LCFS/LIFO  scheduling.  5Marks
7)    Explain the following Non-preemptive scheduling: i) SJF scheduling. 5Marks ii) Priority Based scheduling. 5Marks
8)    Explain the following preemptive scheduling Process: i) Preemptive SJF scheduling/SRT. 5Marks ii) Round Round (RR) scheduling.  5Marks
9)    Explain Shared Memory Process in detail. 10 Marks
10)    Explain Message Passing system in detail. 10 Marks
11)    What is a deadlock? Explain where deadlock situation can arise and methods to avoid deadlocks. 10 Marks
12)    Explain Dining Philosopher's Problem in detail. 10 Marks
13)    Explain Producer-Consumer/Bounded Buffer Problem. 10 Marks
14)    Explain Task synchronization Techniques. 10 Marks
15)    Describe SEMOPHORE in detail. 10 Marks
16)    Explain the role of Device driver in Embedded OS based Products.And describe the functional and non-functional requirements in using an RTOS. 10 Marks

17)    Three Processes with process ID's P1,P2,P3 with estimated completion time 10,5,7 milliseconds respectively enters the ready queue together in order P1,P2,P3. Calculate the Waiting time and Turn Around Time(TAT) for each process and the Average Waiting time and Turn Around Time(TAT) (Assuming there is no I/O waiting for the processes) in the FIFO scheduling. 10 Marks
18)    Three Processes with process ID's P1,P2,P3 with estimated completion time 6,4,2 milliseconds respectively enters the ready queue together in order P1,P2,P3. Calculate the Waiting time and Turn Around Time(TAT) for each process and the Average Waiting time and Turn Around Time(TAT) (Assuming there is no I/O waiting for the processes) in RR algorithm with Time slice = 2ms. 10 Marks
19)    Three Processes with process ID's P1,P2,P3 with estimated completion time 12,10,2 milliseconds respectively enters the ready queue together in order P2,P3,P1. A new process P4 with estimated execution completion time 4 milliseconds enters the ready queue enters the ready queue after 8 milliseconds. Calculate the Waiting time and Turn Around Time(TAT) for each process and the Average Waiting time and Turn Around Time(TAT) (Assuming there is no I/O waiting for the processes) in the Non-preemptive LIFO scheduling. 10 Marks.
20)    Three Processes with process ID's P1,P2,P3 with estimated completion time6,8,2
milliseconds respectively enters the ready queue together . A new process P4 with estimated execution completion time 4 milliseconds enters the ready queue enters the ready queue after 1 milliseconds. Calculate the Waiting time and Turn Around Time(TAT) for each process and the Average Waiting time and Turn Around Time(TAT) (Assuming there is no I/O waiting for the processes) in the Non-preemptive SJF scheduling. 10 Marks.
21)    Three Processes with process ID's P1,P2,P3 with estimated completion time 4,6,5
milliseconds and priorities 1,0,3 (0--Highest priority and 3-- Lowest priority) respectively enters the ready queue together. A new process P4 with estimated execution completion time 6 milliseconds and priority 2 enters the ready queue enters the ready queue after 5 milliseconds. Calculate the Waiting time and Turn Around Time(TAT) for each process and the Average Waiting time and Turn Around Time(TAT) (Assuming there is no I/O waiting for the processes) in the Non-preemptive Priority-Based scheduling. 10 Marks.
22)    Three Processes with process ID's P1,P2,P3 with estimated completion time 4,6,5
milliseconds and priorities 1,0,3 (0--Highest priority and 3-- Lowest priority) respectively enters the ready queue together. Calculate the Waiting time and Turn Around Time(TAT) for each process and the Average Waiting time and Turn Around Time(TAT) (Assuming there is no I/O waiting for the processes) in the Preemptive Priority-Based scheduling. 10 Marks.
23) Three Processes with process ID's P1,P2,P3 with estimated completion time 12,10,6
milliseconds respectively enters the ready queue together . A new process P4 with estimated execution completion time 2 milliseconds enters the ready queue enters the ready queue after 3 milliseconds. Calculate the Waiting time and Turn Around Time(TAT) for each process and the Average Waiting time and Turn Around Time(TAT) (Assuming there is no I/O waiting for the processes) in the SRT scheduling. 10 Marks.


                        UNIT – 6 RTOS-II

    1) CASE STUDY: Telephone Answering Machine. Write the Theory of operation and             requirements along with detailed specifications. 10 Marks
    2) Explain briefly the procedure of evaluating operating system performance. 10 Marks
    3) Describe various interprocess communication mechanisms. 10 Marks
    4) Explain Rate-Monotonic scheduling under priority based scheduling. 10 Marks
    5) Explain Earliest-Deadline-First scheduling under priority based scheduling. 10 Marks
    6) Describe various platforms under preemptive Real-time operating systems and              explain any two in detail. 10 Marks
    7) Describe the following: I) CPU Metrics 5 Marks  II)Timing requirements on process.              5 Marks
    8) Define Tasks and process. Explain Multirate systems. 10 Marks

Saturday, October 11, 2014

Advanced Computer Architecture-IInd Internal Question Bank

Unit-5

1) Explain the computer structures of SISD, SIMD, MISD and MIMD with a neat diagram.

2) What is distributed shared memory architecture?

3) What is symmetric shared memory architecture? Explain with a block diagram.

4) Explain bus snooping protocols with block diagram.

5) Explain state diagram for a cache block in directory based system.

Unit-6

6) Explain first and second optimization for increasing cache performance.

7) Explain the Third optimization in detail.

8) Explain the Fourth optimization in detail of a cache performance.

9) Explain the Fifth optimization in detail.

10) Explain the Sixth optimization in detail.

Wednesday, September 10, 2014

Question_Bank-Advanced_Computer_Architecture(ACA)-VTU-VII-A&B


Question Bank- ACA- VII A & B- 1st Internal

1) Explain various classes of computers? And the 7 dimensions of ISA?

2) Write a note on recent trends in computer design or explain trends in technology?

3) What is Amdahl’s law? Explain in detail with example?

4) What is trends in performance of parallel computers. Explain in detail.

5) How to measure and report the performance of the parallel computing systems?

6) What is a structural Hazard? Explain with a neat diagram?

7) What is a data hazard? Explain with a neat diagram?

8) What is control hazard? Explain with a neat diagram?

9) Explain the implementation of MIPS pipeline with a neat diagram?

10) What are the types of dependencies? Explain the data dependencies?

11) Explain the name dependencies?

12) Explain the control dependencies?

Wednesday, May 7, 2014

System Simulation and Modelling - IIIrd internal Question Bank

Final QB:

Download

Reduced number of questions from 19 to 14. They are from unit 6 and 8. 4 questions in unit 6 and 10 from unit 8.

Friday, March 28, 2014

System Simulation and Modeling - IInd Internal Question Bank

SYSTEM MODELLING & SIMULATION QUESTION BANK II INTERNALS
VIII CS 10CS82

Unit-III

1. Explain the following in Discrete Distributions:
a) Bernoulli’s Distributions/Trials. (5)
b) Binomial Distributions (5).

2. Generate Three Poisson variates with mean α=0.2.Compute e-α. Generate Three Random
  Numbers and compute the results in Tabular form.

3. a) Explain Uniform Distributions in detail(5).
b) Explain Weibull Distributions in detail(5).

4. Explain Poisson process.

5. a) Explain the procedure for generating a Poisson random variate (5).
b) Explain Triangular distributions (5).

6. Explain the following Continuous Distributions:
a) Log Normal Distributions.(5)
b) Triangular Distributions.(5)

7. Explain the following Continuous Distributions:
a) Gamma Distributions.(5)
b) Erlang Distributions.(5)

8. Explain the following Continuous Distributions:
a) Uniform Distributions. (5)
b) Exponential Distributions. (5)

9. Explain Empirical Distributions.

Unit-V

1a) Explain the Properties of Random Numbers?
b) Explain the Generation of Pseudo-Random Numbers?

2. Explain Various Tests for Random Numbers?

3. The sequence of numbers 0.44,0.81,0.14,0.05,0.93 has been generated. Use kolmogorov- smirnov test with alpha=0.05 to determine if the hypothesis that its number are uniformly distributed on interval (0,1) can be rejected. First the numbers must be ranked fro smallest to largest. Compare F(x) and Sn (x) on a graph?

4. Test for whether the 3rd,8th 13th and so on, numbers in the sequence at the beginning are autocorrelated using alpha=0.05.Here, i=3(beginning with the third number),m=5(every five numbers),N=30(30 numbers n the sequence),and M=4(Largest integer such that 3+(M+1)5<=30).

0.12 0.01 0.23 0.28 0.89 0.31 0.64 0.28 0.83 0.93
0.99 0.15 0.33 0.35 0.91 0.41 0.60 0.27 0.75 0.88
0.68 0.49 0.05 0.43 0.95 0.58 0.19 0.36 0.69 0.87

5. Differentiate between Chi-square and K-S Test?

6. Using χ2(Chi Square) test, Test for Hypothesis that the data given follows Uniform Distribution at alpha=0.05.The Critical value is 16.9

O(i)
8
8
10
9
12
8
10
14
10
11

7. Explain in detail the Inverse Transform technique for Exponential Distributions (10).