Advanced Computer Architecture-Dec/Jan2015-VTU

Dec/Jan2015-10CS74

Advanced Computer Architecture

Time:3hrs Max.                                                                                        Marks:100

PART-A

1. a) Define Computer Architecture. Illustrate the seven dimensions of an ISA.
   b) Find the die yield for dies that are 1.5 cm on a side and 1.0 cm on a side assuming a defect density of 0.4 per cm2 and α is 4.
   c) Define amdahl's law. Derive an expression for CPU clock as a function of instruction count. Clocks per instruction and clock cycle time.
2. a) What is pipelining? With neat diagram, explain the classic five stage pipeline for RISC processor.
   b) Consider unpipelined processor. Assume that it has a 1ns clock cycle and that it uses 4 cycles for ALU operations and branches and 5 cycles for memory operations. Assume that the relative frequencies of these operations 40%, 20% and 40% respectively. Suppose that due to clock skew and setup, pipelining the processor adds 0.2ns of overhead to the clock. Ignoring any latency impact, how much speedup in the instruction execution rate will be gain from pipeline?
   c) Explain different techniques in reducing pipeline branch penalties.
3. a) Explain true data dependence, name dependence and control dependence, with an example.
   b) What is Correlating Predictors? Explain with example.
   c) With a neat diagram give the basic structure of Tomasulo based MIPS FP unit and explain various fields of reservation station.
4. a) Explain exploiting ILP using dynamic scheduling multiple issue and speculation.
   b) Explain Pentium 4 pipeline supporting multiple issue with speculation.
   c) Explain in detail, Branch-Target buffers.
   PART-B

5. a) Explain the basic schemes for enforcing coherence in a shared memory multiprocessor system.
   b) Explain the taxonomy of parallel architecture.
   c) Suppose you want to achieve a speedup of 80 with 100 processors. What fraction of the original computation can be sequential?
6. a) Explain four memory hierarchy questions, in detail.
   b) Explain in brief, the types of basic cache optimization.
   c) Define Virtual Memory and describe its features.
7. a) Which are the major categories of advanced optimizations of cache performance? Explain any one in detail.
   b) Describe the technique to improve memory performance inside DRAM chip.
   c) Explain the process of protecting via virtual machines.
8. a) Explain detecting and enhancing loop level parallelism for VLIW.
   b) Explain Intel-IA 64 architecture, with a neat diagram.
   c) Write a brief note on predicated instructions.
   
   Accuracy of the above question paper is not guaranteed.
   Here is July,2014 Question Paper.