Advanced Computer Architecture- IIIrd Internal QB

Advanced Computer Architecture- IIIrd Internal QB

Unit-3

1) What are the basic compiler techniques for exposing ILP? Explain briefly.

2) List the steps to unroll the code and schedule.

3) What are the techniques used to reduce branch costs? Explain both static and dynamic branch prediction used for same.

4) Explain the dynamic branch prediction state diagram.
4) What is the drawback of 1-bit dynamic branch prediction method? Clearly state, how it is overcome in 2-bit prediction. Give the state transition diagram of 2-bit predictor.
4) What is dynamic prediction? Draw the state transition diagram for 2-bit prediction scheme?

5) What is correlating predictors? Explain with examples.

  

Unit-6

1) How to protect virtual memory and virtual machines?

2) Explain the six basic cache optimization techniques.

2) Explain the six basic optimizations.

2) Explain the types of basic cache optimization.

2) Explain in brief, the types of basic cache optimization.

2) Briefly explain four basic cache optimization methods.

3) What are the techniques for fast address translation? Explain.

4) With a neat diagram, explain the hypothetical memory hierarchy.

5) Explain block replacement strategies to replace a block, with example when a cache miss occurs.

6) With a diagram, explain organization of data cache in the opteron microprocessor.

7) Assume we have a computer where CPI is 1.0 when all memory accesses hit in the cache.

 The only data accesses are loads and stores, and these total 50% of the instructions. If the miss penalty is 25 cycles and miss rate is 2%, how much faster would the computer be, if all instructions were cache hits?

7) Assume we have a computer where the clocks per instruction (CPI) is 1.0 when all memory accesses hit in the cache. The only data accesses are loads and stores and these total 50% of the instructions. If the mass penalty is 25 clock cycles and the mass rate is 2%, how much faster would the computer be if all instructions were cache hits?

8) Assume that the hit time of a two-way set-associative first-level data chache is 1.1 times faster than a four-way set-associative cache of the same size. The miss rate falls from 0.049 to 0.044 for an8 KB data cache. Assume a hit is 1 clock cycle and that the cache is the critical path for the clock.  

 Assume the miss penalty is 10 clock cycles to the L2 cache for the two-way set-associative cache and that the L2 cache does not miss. Which has the faster average memory access time?

9) Suppose you measure a new DDR3 DIMM to transfer at 16000 MB/sec. What do you think its name will be? What is the clock rate of that DIMM? What is your guess of the name of DRAMs used in that DIMM?

10) Given the data below, what is the impact of second level cache associativity on its mass penalty?

•             Hit time L2 for direct mapped=10 clock cycles

•             Two way set associativity increases hit time by 0.1 clock cycles to 10.1 

               clock cycles.

•             Local miss rate L2 for direct mapped = 25%

•             Local miss rate L2 for two-way set associative= 20%

•             Miss penalty L2= 200 clock cycles.